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Design and Analysis of Sequential Circuit for Leakage Power Reduction using Stacking Effect

Author(s):

Neha Jassi , swami devi dyal institute of technology and enggineering; Arti Goel, sddite

Keywords:

Dynamic Power, Delay, Low Power Design

Abstract

The rapid growth in semiconductor device industry has led to the development of high Performance potable systems with improve reliability. In such applications, it is extremely important to minimize current consumption due to the limited availability of battery Power. Consequently, power dissipation is becoming recognized as a top priority issue for VLSI circuit design. Leakage power makes up to 50% of the total power consumption in today's high performance microprocessors. Therefore leakage power reduction becomes the key to a low power design. Leakage power dissipation is the power dissipated by the circuit when it is in Sleep mode or standby mode. A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only Source. of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable system.

Other Details

Paper ID: IJSRDV2I7068
Published in: Volume : 2, Issue : 7
Publication Date: 01/10/2014
Page(s): 186-189

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