A Review of Low-Energy 1-Bit Full Adder Techniques for Power Deprived Applications |
Author(s): |
| Pawan Kumar Mishra , JSSATE, NOIDA; Himani Mittal, JSSATE, NOIDA |
Keywords: |
| Deep submicron, SERF, 1-bit full adder low power |
Abstract |
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In this work a comparison and study of different low power 1-bit full adder techniques at deep submicron technologies is carried out. The study concentrates in the crucial factors which determine the applicability of the design for particular applications. The comparison of different adders has been carried out on the basis of these parameters i.e. delay, power consumption, output swing, PDP etc. The comparison is carried out between designs with low device count. On the basis of comparison a conclusion has been drawn in which the shortcomings of present designs have been discussed with future possibilities of improvement. The designs compared are TGA, SERF and modified SERF. |
Other Details |
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Paper ID: IJSRDV2I9179 Published in: Volume : 2, Issue : 9 Publication Date: 01/12/2014 Page(s): 218-220 |
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