Switching Loss Reduction in a Cascaded Multilevel Inverter With Reduced Number of Components

A new general cascaded multilevel inverter with single carrier level shift PWM is proposed in this paper. The proposed topology requires a lesser number of dc voltage sources and power switches and consists of lower blocking voltage on switches, which results in decreased complexity and total cost of the inverter. These abilities obtained within comparing the proposed topology with the conventional topologies. Moreover, a new algorithm to determine the magnitude of dc voltage sources is proposed. In which only one carrier signal is used and compared with reference signal. Depends upon the level or RMS value of output voltage, the level of carrier signal is determined. Based on the level determined, the carrier signal is shifted and compared with reference signal. The proposed technique completely eliminates the switching transition in the lower levels. So it reduces switching loss and also improves the power quality. The performance and functional accuracy of the proposed topology using the new algorithm in generating all voltage levels for a 31-level inverter are confirmed by MATLAB simulation and experimental results.