Efficiency and Area Reduction for a PRNG Frame Work Based on Well Method

WELL method mainly describes that the 7.1 fold faster technique is inbuilt to increase the efficiency and reduce the area. The proposed architecture also implemented on targeting different device for the comparison of other types of PRNG. Interleaver sequence technique is used. A large number of research is made on PRNG compared with the MT algorithm specified for less than 423 MHz of frequency range. Now a days the recent communication technique is made for the WELL method along with the PRNG to achieve the high frequency range than the 423MHz. A resource – efficient hardware architecture for WELL with a throughput of one sample per cycle. The Well Equidistributed Long-period Linear (WELL) algorithm is proven to have better characteristics than the Mersenne Twister (MT), one of the most widely used long-period pseudo-random number generators (PRNGs). In this paper, we propose a hardware architecture for efficient implementation of WELL. Our design achieves a throughput of 1 sample-per-cycle and runs as fast as 423MHz on a Xilinx XC6VLX240T FPGA Furthermore, we design a software/hardware framework that is capable of dividing the WELL stream into an arbitrary number of independent parallel sub-streams. With support from software, this framework can obtain speedup roughly proportional to the number of parallel cores. We also apply our framework to a Monte-Carlo simulation for estimating p. Experimental results verify the correctness of our framework as well as the better characteristics of the WELL algorithm.