Design of FFT Architecture for Real Valued Signals using Radix 2^5 Algorithm

A novel approach to develop a Fast Fourier Transform (FFT) for real valued signal using Radix 25 algorithm is proposed in this paper. Methodology is to modify the flow graph of the FFT architecture. Redundant components are replaced by the imaginary computations. Hardware complexity of this RFFT architecture will be low compared to Radix 23 and Radix 24 algorithms in terms of adder, multiplier and delay. This proposed architecture maximizes utilization of hardware with no redundant computation. RFFT is used for real time applications and also in portable devices where low power consumption is the main requirement. So accordingly Vedic multiplier and carry propagate adder has been used in the proposed work. These adder and multiplier will help to reduce the delay of the system. So accordingly the system will be fast, which is a must have feature for the portable and real time systems.