Design of Double Precision Floating Point Multiplier usingVHDL |
Author(s): |
| Namrata R. Patel , SANKALCHAND PATEL COLLEGE OF ENGINEERING, VISNAGAR.; Prof. Hetal G. Bhatt, SANKALCHAND PATEL COLLEGE OF ENGINEERING,VISNAGAR. |
Keywords: |
| Double precision, Floating point, Multiplier, FPGA, IEEE-754 standard |
Abstract |
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Floating point arithmetic is widely used in many areas, especially in scientific computation and signal processing. Now a day the main applications of floating points are in the field of medical imaging, biometrics, motion capture and audio applications. Multipliers play an important role in digital signal processing and other applications. A system’s performance is generally determined by the performance of the multiplier, because the multiplier is the slowest element in the system. The proposed design is compliant with IEEE-754 format and handles overflow, underflow, rounding and exception conditions. The design achieved the operating frequency of 35.89 MHz. |
Other Details |
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Paper ID: IJSRDV3I30644 Published in: Volume : 3, Issue : 3 Publication Date: 01/06/2015 Page(s): 1356-1358 |
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