A CMOS Phase Locked Loop based PWM Generator using 90nm Technology |
Author(s): |
| B K Arun Teja , VIT UNIVERSITY,VELLORE; K Sai Ravi Teja, VIT UNIVERSITY,VELLORE |
Keywords: |
| PWM, Duty Cycle, Phase Detector, Class D, Phase Locked Loops, Pulse Width Modulation |
Abstract |
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A CMOS class D phase locked loop based PWM generator is presented in this paper. The implementation is done in a 90nm CMOS process using CADENCE tool. The architecture in this project eliminates the requirements for a high-quality carrier generator and a high-speed voltage comparator that are often required in PWM implementations. Voltage comparison is replaced by Phase comparison and precise ramp signal is replaced by Reference clock. Phase comparison is fast and accurate when compared to voltage comparison. Reference clock does not have a stringent linearity requirement like precise ramp signal. With this we can achieve a PWM signal with 70% duty cycle. |
Other Details |
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Paper ID: IJSRDV3I60300 Published in: Volume : 3, Issue : 6 Publication Date: 01/09/2015 Page(s): 515-519 |
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