Design of Low Power Area Efficient Pulsed Latches Based Shift Register

The timing elements and clock interconnection Networks such as flip-flops and latches, is One of the most power consuming components in modern very large Scale integration (VLSI) system. The area, power and transistor count will compared and designed using several latches and flip flop stages. Flip Flop is a circuit which is used to store state information. Power consumption is one of the main objectives in designing a flip flop. The flip flops used in designing are Hybrid Latch Flip Flop (HLFF), explicit- pulsed data-close-to-output flip-flop (ep-DCO) and Adaptive-Coupling Redundant Flip-Flop (ACFF). Compare pulse triggered latches based on transistor count, power and layout area. Constructing shift registers by using conditional capture pulsed latches instead of normal flipflops, because a pulsed latch is much smaller than a flip-flop. All the latches and flip flop designs are made by using 90nm technology in DSCH2 schematic tool and MICROWIND design tool.