A Low Complexity and Highly Robust Multiplier Design Using Adaptive Hold Logic

This project deals with Aging Aware Reliable multiplier design with adaptive hold logic, Digital multipliers is one of the major unit in arithmetic functional units. The overall performance of the AHL systems depends on the throughput of the multiplier. Even though the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias voltage, it leads in the increasing threshold voltage of the pMOS transistor and it will reduce the speed of the multiplier design. Hence like this the positive bias temperature instability occurs when an nMOS transistor is under positive bias. These two effects degrade transistor speed, and in the long term the system may fail due to timing violations. Hence it is important to design reliable high performance multipliers. In this project we propose an aging aware multiplier design with an adaptive hold logic circuit. By this the multiplier is able to provide higher throughput through the variable latency and can adjust adaptive hold logic circuit to mitigate performance degradation that is due to aging effect.