Simulation and Synthesis of Various Modules of Satellite Modem using Synopsys Flow

There are various satellite ground terminals needs to be designed with reduced weight, volume, power and manufacturing cost. Modem is one of the major constitute of satellite terminal. To achieve high form factor without compromising performance a single chip solution for digital modem is developed. With the growing complexity of VLSI circuitry, the ability to perform both the time and cost effective design and test of IC devices has become increasingly difficult. Design Compiler is EDA tool used for synthesis of the design. Design Compiler reads design file in VHDL/verilog format & translate into gate level netlist using technology library. Functional simulation of modem is performed in VCS. The basics of VCS and Design Compiler is discussed in this paper. Simulation results of NCO which is a module of satellite modem using Synopsys VCS G-2012.09-SP1. Synthesis reports and gate level netlist has been generated of the same using synopsys design compiler G-2012.06-SP5-1. Other modules like Scrambler, Differential Encoder, Modulator, Demodulator, Descrambler, Differential Decoder, Viterbi Decoder are also simulated and synthesized using VCS and Design Compiler.