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Design and Evaluation of High Speed Parallel Multiplier Using Low Power Data Compressors

Author(s):

J.BERYL JANCY , FRANCIS XAVIER ENGINEERING COLLEGE,VANNARPETTAI,TIRUNELVELI.; Miss. A.Benila , FRANCIS XAVIER ENGINEERING COLLEGE,VANNARPETTAI,TIRUNELVELI.

Keywords:

Parallel multiplier, Compressor, low power, high speed

Abstract

A Parallel multiplier using approximate compressors are proposed in this paper. The two new approximate 4-2 compressors are proposes that the simplified compressors have better power consumption than the optimized 4-2 compressor existing designs. These approximate compressors are then used in the restoration module of a Parallel multiplier. Four different schemes for utilizing the proposed approximate compressors are proposed and analyzed for a Parallel multiplier.

Other Details

Paper ID: IJSRDV4I31470
Published in: Volume : 4, Issue : 3
Publication Date: 01/06/2016
Page(s): 1799-1803

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