Packet Switched Wormhole Router Design and Low Latency Adapter Design for NOC Architecture and Its FPGA Implementation

As growth in an integrated technology the number of processing elements used in single chip increases, which causes the interconnection of elements in a chip is complex using conventional bus based system. A network on chip (NoC) is new paradigm for communication between components in a system on chip. Other aspect is the speed of communication between nodes gets reduced, for this reason various routing algorithms and switching techniques are introduced, amongst selection is a main criteria. In this project wormhole switching with XY routing algorithm is used. The speed of the communication between components is increased though adapter design. In this project wishbone architecture is used to communicate between nodes. The Mesh topology is used to reduce the network congestion problems in NoC. IP cores and adapter are designed using Wishbone Protocol to communicate with NoC nodes. The design will be implemented using Artix-7 FPGA board. ISim tool is used to simulate and test the system.