Design of High Performance Systolic Parallel and Serial Multipliers |
Author(s): |
| E. Karnakar , PATHFINDER ENGINEERING COLLEGE; M. Srujana, PATHFINDER ENGINEERING COLLEGE |
Keywords: |
| Digit serial, Bit parallel, NIST, GF multipliers |
Abstract |
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The cryptograpy systems are mostly performed with the finite field multipliers which have high performance and low latency but such multipliers not so redundant over GF(2m) NIST pentonomials. Here we are presenting two types of high performance multipliers such as bit parallel and digit serial systolic multipliers. The proposed design mostly depends on the several parallel arrays in 2D(2-dimensional) that is BP1 with low critical path and the serial systolic multiplier sDS1 also depend on the vertical parallel arrays in the 2-dimensional series. For high performance we are designing the two different multipliers which are BP-II and DS- II. Both these multipliers are designed with several Processing elments(PE’s). These proposed multipliers should contain less delay and high performance compare with the existed designs. |
Other Details |
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Paper ID: IJSRDV4I40470 Published in: Volume : 4, Issue : 4 Publication Date: 01/07/2016 Page(s): 488-492 |
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