Implementation of Radar Signal Processing Model on Tiled System on Chip

The radar systems requires high processing capabilities. The signal processing chain applied to the received echo requires high-computing power to extract target information in real time. In order to meet the requirements multiprocessor systems on chip (MPSoC) [1] have become the processing platform of choice. They provide unmatched signal processing at very low power levels for radar and avionics, as well as software defined radios (SDR), imaging and video applications that often accompany radar and avionics. The objective is to implement a radar signal processing chain on multiprocessor heterogeneous tiled System on Chip (SoC) architecture which uses multiple programmable processor tiles with different functionalities that operates concurrently. The multiprocessor system on chip consists DSP blocks such as multiplier/adder and hardware accelerators. The hardware accelerator is a component that works together with the processor and executes key functions much faster than the processor.