FPGA Implementation of Three Stage Pipelining

Pipeline is a technique used to increase the instruction throughput (the number of instructions that can be executed in a unit of time). Pipelining doesn't reduce the time it takes to complete an instruction; it increases the number of instructions that can be processed at once, thus reducing the delay between completed instructions. The fundamental idea is to split the processing of a computer instruction into a series of independent steps, with storage at the end of each step. This allows the computer's control circuitry to issue instructions at the processing rate of the slowest step, which is much faster than the time needed to perform all steps at once. The term pipeline refers to the fact that each step is carrying data at once (like water), and each step is connected to the next (like the links of a pipe.) The terms, "Fetch, Decode, and execute" that become common usage in pipelining. In fetch, the instruction is fetched from the memory. In decode, instruction is decoded and in execute, it is executed i.e. result is got from the ALU. Implementation of three stage pipelining has been done taking the ALU design.