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Design of High Speed 32-Bit Single Precision Floating Point Complex Multiplier using Vedic Mathematics


Miss. Ashwini B. Kewate , B.D.C.O.E.; Prof. P. R. Indurkar, B.D.C.O.E.; Prof. A. W. Hinganikar, B.D.C.O.E.


Complex Multiplier, Vedic Mathematics, IEEE 754 Single Precision Standard Format Urdhva Tiryagbhyam


This paper describes the design of 32-bit single precision floating point complex multiplier using Vedic mathematics. Multipliers are key components of many high performance systems such as microprocessors, FIR filters, digital signal processors, etc. Performance of a system is generally determined by the performance of the multiplier. Complex number operations are the backbone of many digital signal processing algorithms, which mostly depend on extensive number of multiplications. Complex multiplication is of immense importance in Digital Signal Processing (DSP) and Image Processing (IP). The IEEE 754 standard provides the format for representation of Binary Floating point numbers in computers. The Binary Floating point numbers are represented in Single and Double formats. Vedic mathematics is the Indian system of mathematics which is mainly based on 16 Sutras. The “Urdhva Tiryagbhyam” sutra is used for the design. 32-bit adder, sub-tractor, 24bit Vedic multiplier and 32 bit floating point complex multiplier are designed. All the modules in the design are coded in VHDL Finally. Simulation of the design is done in XILINX 14.5i ISE Simulator.

Other Details

Paper ID: IJSRDV4I50790
Published in: Volume : 4, Issue : 5
Publication Date: 01/08/2016
Page(s): 1466-1469

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