LDO Regulator using Comparator in 0.9 µm CMOS Process |
Author(s): |
P. Rajesh , RATHINAM TECHNICAL CAMPUS; K. Muthusamy , RATHINAM TECHNICAL CAMPUS |
Keywords: |
EA, LDO, MOS, Bandwidth |
Abstract |
A low-voltage low-dropout (LDO) regulator that converts an input of 1 V to an output of 0.85–0.5 V, with 90-nm CMOS technology is proposed. A simple symmetric operational transconductance amplifier is used as the error amplifier (EA), with a current splitting technique adopted to boost the gain. This also enhances the closed-loop bandwidth of the LDO regulator. In the rail-to-rail output stage of the EA, a power noise cancellation mechanism is formed, minimizing the size of the power MOS transistor. Furthermore, a fast responding transient accelerator is designed through the reuse of parts of the EA. These advantages allow the proposed LDO regulator to operate over a wide range of operating conditions while achieving 99.94% current efficiency, a 28-mV output variation for a 0–100 mA load transient, and a power supply rejection of roughly 50 dB over 0–100 kHz. The area of the proposed LDO regulator is only 0.0041 mm2, because of the compact architecture. And the LDO regulator is fed as an input supply to the comparator. |
Other Details |
Paper ID: IJSRDV5I120044 Published in: Volume : 5, Issue : 12 Publication Date: 01/03/2018 Page(s): 314-317 |
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