Analysis of the Effect of Temperature and Supply Voltage Variations on Leakage Power in Conventional 6T-SRAM Cell at Different Process Corners

deep-submicron processes, Leakage power becomes critical factor. In recent technologies, leakage power is a major concern, as it impacts battery lifetime. When memory cell runs in standby mode, power dissipation occurs. Due to maximize power dissipation, battery life decreases in portable devices. In this paper, we have performed simulation and analysis of a conventional 6T SRAM Bit-cell thereafter a comparative analysis is being performed for the leakage power at 45nm and 32nm CMOS technology at different process corners using HSPICE circuit simulator. Effect of temperature and voltage variations on leakage power are also explored in this paper to create effect as a practical environment. When we kept VDD=1v, 45nm based 6T SRAM cell gives 50.27% minimum leakage power at SS corner as compare to 32nm based 6T SRAM cell significantly.