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Low Power Conventional Level Shifter (CLS) Design Comparison with 6, 8 and 10 Transistors

Author(s):

JBS Loknath , MRECM; J. Naga Raju, MLR Institute of Technology

Keywords:

CMOS, Conventional Level Shifter, CMOS Technology, Power, Noise Voltage, Leakage Voltage

Abstract

The paper mainly focuses on a new design of Low Power Conventional level shifter with a 45nm CMOS technology and simulated in Symica tool. The Conventional level shifters are designed with the six transistors, eight transistors and ten transistors. The parameters being observed for the proposed circuit design are average power dissipation, average noise and leakage voltage. This type of conventional level shifter requires two different voltage supplies: the input logic signal voltage supply (VDD Low) and output logic signal voltage supply (VDD High). The voltages are used for the proposed working of the design circuits are from 0.2 volt to 0.7 volt. Level shifter circuits are more commonly used for an interface with different voltage domain in System on chip (SoC) and modern ICs. It has been known that conventional level shifter has the ability to achieve low power operation and converts high voltage digital input signals to high voltage digital output signals. A conventional level shifter is capable of ability to with stand extremely low voltage input. It is used to change or shift any voltage level to a desired required voltage level. The level shifter satisfies the required needs of lower power application systems and also used for ICs and system on chip (SoC) modules.

Other Details

Paper ID: IJSRDV5I80404
Published in: Volume : 5, Issue : 8
Publication Date: 01/11/2017
Page(s): 626-628

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