Design and Implementation of High Speed and Low Power Wallace Multiplier |
Author(s): |
| Mr. Bharat H. Nagpara , C. U. Shah College of Engineering and Technology; Mr. S. D. Madhar, C. U. Shah Technical Institute of Diploma Studies |
Keywords: |
| Flow of Wallace Tree, 8X8 Bit Wallace Architecture, Simulation Results, Comparison |
Abstract |
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8x8 bit Multiplier architecture based on Wallace Tree, which is efficient in terms of power and regularity without increase in delay and area. The idea involves the generation of partial products in parallel using AND gates. The addition of partial products is done using Wallace tree, which is hierarchal, divided into levels. There will be a reduction in the power consumption, since power is provided only to the level that is involved in computation. The proposed 8x8-bit Wallace tree Multiplier has been designed using proposed compressors and the power consumption results are low and also less delay has been observed. The proposed Wallace tree Multiplier using these compressors achieves significant amount of less power than conventional Wallace tree Multiplier. The designs are implemented and power results are obtained using TANNER EDA 15.0 v tool. |
Other Details |
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Paper ID: IJSRDV6I40336 Published in: Volume : 6, Issue : 4 Publication Date: 01/07/2018 Page(s): 679-681 |
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