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Design and Analysis of Floating Point Arithmetic Adder


Neelam Sharma , VNS group of institution Bhopal; Anil Khandelwal, VVNS group of institution Bhopal


VHDL, Comparator, Add/Sub, Floating Point Adder


Floating-point addition is the most frequent floating-point operation and accounts for almost half of the scientific operation. Therefore, Floating-point addition is a costly operation in terms of hardware and timing as it needs different types of building blocks with variable latency. In floating-point addition implementations, latency is the overall performance bottleneck. A lot of research has investigated optimization of floating-point units for area, delay and power consumption in hardware. While the others will be described shortly the result carried out on Xilinx in term of area and delay. This paper presents the highly efficient floating adder for effective way to present fast addition.

Other Details

Paper ID: IJSRDV6I50008
Published in: Volume : 6, Issue : 5
Publication Date: 01/08/2018
Page(s): 49-52

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