High Impact Factor : 4.396 icon | Submit Manuscript Online icon |

An Efficient Framework Design for Low Power Redundant Binary Multiplier

Author(s):

Arun Sekar R , SNS COLLEGE OF TECHNOLOGY; Sasipriya S, SRI KRISHNA COLLEGE OF ENGINEERING AND TECHNOLOGY

Keywords:

Redundant Binary Representation (RBR), Redundant Multipliers, Signal- Flow Graph (SFG), Processor-Space Flow Graph (PSFG), Redundant Binary Partial Product Generator

Abstract

In versatile hardware diminishing area and power utilization are enter factors in expanding convey ability and battery life. Indeed, even in servers and personal computers, control utilization is a critical plan requirement. Here another Redundant Binary altered fractional item generator is proposed, it evacuates the additional Error Correcting Word and thus, it spares one excess double incomplete item aggregation arrange. A Redundant Binary Representation (RBR) is a numeral framework that utilizations a greater number of bits than expected to speak to a solitary paired digit with the goal that most numbers have a few portrayals. A RBR is not at all like normal twofold numeral frameworks, including two's supplement, which utilize a solitary piece for every digit. A considerable lot of a RBR's properties contrast from those of general parallel portrayal frameworks. In particular, a RBR permits expansion without utilizing a commonplace convey. At the point when contrasted with non-repetitive portrayal, a RBR makes bitwise consistent activity slower, yet math tasks are quicker when a more prominent piece width is utilized. Normally, every digit has its very own sign that isn't really the equivalent as the indication of the number spoke to. At the point when digits have signs, that RBR is additionally a marked digit portrayal. Consequently, the excess paired changed incomplete item generator creates less halfway item pushes than a traditional repetitive double Modified Booth Encoding multiplier. Reenactment results demonstrate that the repetitive twofold altered halfway item generator based outlines altogether enhance the territory and power utilization when the word length of every operand in the multiplier is no less than 32 bits; these decreases over past Normal Binary multiplier plans acquire in an unobtrusive defer increment (fractional item roughly 5%). The power-postpone item can be diminished by up to 59% utilizing the proposed excess double multipliers when contrasted and existing repetitive twofold multipliers.

Other Details

Paper ID: IJSRDV6I80173
Published in: Volume : 6, Issue : 8
Publication Date: 01/11/2018
Page(s): 416-421

Article Preview

Download Article