Reconfigurable Architecture for Internet Packet Filter |
Author(s): |
Navinkumar Gajakumar Patil , CDAC; Hemant Jeevan Magadum, CDAC; Lakshmaiah Alluri, CDAC |
Keywords: |
Network security, firewall, packet filter, linear search, Field Programmable Gate Array (FPGA) |
Abstract |
Internet packet filer is one of the most widely used security approach in networking. Now a days the speed of internet is increases so, there is demand for high speed packet classification engine. Most of the available packet classifier engines are based on Ternary Content Addressable Memory (TCAM). This provide the higher throughput at the cost of large resource and high power consumption. Alternative is the linear search algorithm. It is less complex and consume less power but the throughput of this is less. It has most predictable behavior. When there is moderate number of filter rules then linear search algorithm is used. The proposed architecture is modified version of linear filter algorithm. This shows 3 times higher throughput than linear search. Also, it requires small amount of FPGA resources. This packet filter is designed in Verilog and tested on Xilinx Zynq 7000 series FPGA with 30 complex filter rules based on standard five header fields. The proposed architecture works on maximum operating frequency of 215.5 MHz. It supports 1 Gbps internet connection with throughput of 21.55 Mpps (Million packets per second). |
Other Details |
Paper ID: IJSRDV7I100401 Published in: Volume : 7, Issue : 10 Publication Date: 01/01/2020 Page(s): 665-669 |
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