Low Power Excavating the Hidden Parallelism inside DRAM Architectures with Buffered Compares

I propose the approach called buffered compares, a less-invasive processing-in-memory solution that can be used with existing processor memory interfaces such as DDR3/4 with minimum changes. The design is based on observation that multibank architecture, a key feature of main memory Dynamic RAM devices, can be used to provide huge internal bandwidth without any modification. i place a small buffer and a simple ALU per bank, define a set of new DRAM commands to fill the buffer and feed the data to the ALU, and return the result for a set of commands (not for each command) to the host memory controller. By exploring the under-utilized internal bandwidth using ‘compare-n-op’ operations, which are frequently used in many applications, i not only reduce the level of energy inefficient processor–memory communication, but also accelerate the computation of big data processing used by utilizing parallelism of the buffered compare blocks in Dynamic RAM banks. i present two versions of buffered compare architecture full scale architecture and reduced architecture in trade of performance and power. The experimental results show that our solution significantly improves the performance and efficiency of the system on the tested tasks.