Area and Power Efficient Design of Serial Parallel Multiplier

Highly efficient arithmetic operations are necessary to realize the specified performance in many real-time systems and digital image processing applications. In all these applications, one among the important arithmetic operations frequently performed is to multiply and accumulate with small computational time. In this, a serial parallel multiplier is presented. A serial-parallel multiplier is employed for accelerating applications like digital filters, artificial neural networks, and other machine earning algorithms. The simulation is based on VLSI technology. A multiplexer circuit is used as decision maker so that throughput and latency are improved for a subset of multiplier values. Coding can be done using VHDL and simulation can be verified using Xilinx ISE Design Suite. This method presents a decision maker block. The proposed method can reduce the hardware and ensure the results along with area compaction and high speed. High speed and low power MAC unit is utmost requirement of today is VLSI systems and digital signal processing applications like FFT, Finite impulse response filters, convolution etc. To reduce significant power consumption it is good to scale back the amount of operation thereby reducing dynamic power which may be a major a part of total power consumption. So the need of high speed and low power multiplier has increased.