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A New Implementation of Minimum Leakage with Improved Performance SRAM Architecture using CMOS VLSI Circuits


Saraswati M , Govt. Engg. College Raichur, Karnataka; Dr. K. Srinivasa Rao, TRR College of Engineering, Hyderabad; Dr. D. Sreenivasa Rao, JNTU, Hyderabad


SRAM, Deep Submicron Technology, Sub Threshold Leakage Power and LLIP_SRAM


The growing demand for high integrity VLSI circuits, the leakage current in deep sub-micron CMOS technology is a major challenge. In deep submicron technologies, leakage power becomes a key parameter for a minimum leakage power design. Emerging battery-operated applications on one hand and shrinking technology of deep submicron on the other hand, leakage power dissipation is playing a significant role in the total power dissipation as threshold voltage scaled down. Due to the trade-off between power, area and performance, various efforts have been done. In this paper, our concentration is mainly based on minimizing the leakage power dissipation with improvement in the performance of the VLSI circuits. Here we proposed a Novel SRAM architecture called Low-Leakage, Improved-Performance (LLIP) SRAM. In this paper we designed the New SRAM architecture with newly proposed techniques and compare this one with other techniques. We observed that the total power consumption is reduced with improved performance. Here the total architecture is designed with 120nm technology.

Other Details

Paper ID: NCACCP009
Published in: Conference 8 : NCACC-2016
Publication Date: 01/10/2016
Page(s): 168-173

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