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UVM Based Verification Environment for Performance Evaluation of DDR4 SDRAM using Memory Controller


Nausha Kotia , GTU; Prashant Karandikar, Aurora Copper Systems LLP, Pune;


UVM, Verification Environment, TLM, AXI4, DDR4


In digital Design, Verification plays a vital role as most of the time is engaged in verification. So ASIC or SOC verification companies adopted several methodologies for re-usability purpose. The latest methodology adopted is UVM due to its advantages. This paper exhibits Performance checking of DDR4 memory and controller using UVM based on work load, i.e. achieved at RTL level with the use of Scheduling algorithm. To verify the functionality and timing accuracy of memory controller IP, test-bench is constructed at TLM level.

Other Details

Published in: Conference 10 : NCACSET 2017
Publication Date: 06/05/2017
Page(s): 160-165

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