Design of Three Stage Dynamic Comparator with Tail Transistor using 20nm FinFET Modified to Transmission Gate Based Clock Gating Technique

According to this article, one of the key disadvantages is excessive power consumption and offset in CMOS based comparators. At scale down technology, CMOS suffers with short channel effect and leakage current. To address these challenges, FinFET technology is used in three stage dynamic comparators instead of traditional circuit designs. The energy efficiency of FinFET-based dynamic comparators is higher than that of CMOS, and the short channel effect and leakage current are decreased. Furthermore, a new design of FinFET-based three stage dynamic comparators with tail transistors was created and simulated using the cadence virtuoso environment. In this paper, A three stage comparator is presented in a novel architecture. The methodology used for this architecture is Clock Gating technique. In order to achieve fast performance, here the Clock Gating structure is designed based on Transmission Gate Configuration. In conventional three stage comparator, the technology used is FinFET. Here, considering the same technology to develop proposed three stage comparator and its modified architecture. The entire designs are simulated using H-spice software and the comparison of conventional and proposed architectures in terms of power and delay are also presented. According to simulation results, the modified three stage comparator decreases power consumption by 20% it has a 17% energy efficiency.