Enhanced Ripple Suppression in Coupled-Inductor Single-Input Dual-Output DC-DC Converter Systems

This research explores enhanced ripple suppression techniques in Coupled-Inductor Single-Input Dual-Output (CI-SIDO) DC-DC converters, a critical component in power electronics for applications like renewable energy, electric vehicles, and industrial systems. Ripple minimization is essential to improve efficiency, reliability, and system performance. The study introduces an innovative gate pulse shifting strategy to synchronize or desynchronize switching cycles, optimizing current and voltage waveforms and minimizing ripple in both input and output stages. Through a combination of theoretical modeling, MATLAB/Simulink simulations, and experimental validations, the research systematically analyzes the impact of gate pulse angles on performance parameters, including inductor current ripple and output voltage stability. A unified approach for ripple minimization is developed, incorporating sector-based duty ratio optimization and coupled inductor design, which balances flux and minimizes core losses. Experimental results confirm the effectiveness of the proposed methods, achieving up to 92% ripple reduction and expanding the Continuous Conduction Mode (CCM) range. Trade-offs such as increased control complexity and potential cross-regulation are addressed with practical design recommendations. This work advances CI-SIDO converter design by providing a scalable, efficient framework for ripple suppression, with implications for high-demand power electronic systems.