Low-Power Three-Stage Dynamic Comparator with Tail Transistor Using 20-nm FinFET Technology for ADC Applications |
Author(s): |
| Shivraj Suresh Bagale , SVERI’s College of Engineering, Pandharpur, Solapur, Maharashtra, India – 413304 ; Mrs. Shamli Vilas Jagzap, SVERI’s College of Engineering, Pandharpur, Solapur, Maharashtra, India – 413304 ; Onkar Bapuso Deshmukh, SVERI’s College of Engineering, Pandharpur, Solapur, Maharashtra, India – 413304 ; Kartik Raghunath Vaste, SVERI’s College of Engineering, Pandharpur, Solapur, Maharashtra, India – 413304 ; Harshwardhan Yashwant Gaikwad, SVERI’s College of Engineering, Pandharpur, Solapur, Maharashtra, India – 413304 |
Keywords: |
| FinFET, Dynamic Comparator, Analog-to-Digital Converter (ADC), Tail Transistor, Low Power Design |
Abstract |
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Comparators are fundamental components in analog-to-digital converters (ADCs). The overall performance of an ADC strongly depends on the speed, power consumption, and accuracy of the comparator. Traditional CMOS-based comparators suffer from leakage current and short channel effects when implemented in deep submicron technologies. To address these challenges, this paper presents a three-stage dynamic comparator implemented using 20-nm FinFET technology. The proposed design incorporates a tail transistor in the latch stage to reduce power consumption and improve energy efficiency. The circuit was designed and simulated using Cadence Virtuoso with FinFET device models. Simulation results show significant improvement in power efficiency compared with conventional three-stage comparator architectures, making the proposed design suitable for high-speed and low-power ADC applications. |
Other Details |
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Paper ID: IJSRDV14I20035 Published in: Volume : 14, Issue : 2 Publication Date: 01/05/2026 Page(s): 39-42 |
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