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Low Power Design flow using Power Format


Jinal Patel , GTU PG School,Ahemedabad; Ekta Chotai, GTU PG School,Ahmedabad; Naincy Desai, GTU PG School,Ahmedabad; Hemang Patel, State Technological University of Madhya Pradesh, Bhopal (M.P.), India




The demand for portable electronic devices that offers increase in functions, performance at lower costs and smaller sizes increased rapidly. Designing complex SOCs is a challenge, especially at 90 nanometers Technology, where new problems crop up - power efficiency is being the biggest of problems. For different modes we cannot design different operating circuits, better to have technique that will have minimum circuit changes and in all modes it will save power which is wasted. This paper provides some guidelines on how Low Power design using UPF approach can be introduced for a design.

Other Details

Paper ID: IJSRDV1I2046
Published in: Volume : 1, Issue : 2
Publication Date: 01/05/2013
Page(s): 238-241

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