FPGA based BCH Decoder |
Author(s): |
| Prof. Deepti Khurge , L.J.E.I.T, Ahmadabad, Gujarat; Mr. Hardik Sutaria, L.J.E.I.T, Ahmadabad, Gujarat |
Keywords: |
| Finite Fields, Polynomial Basis, Dual Basis, Normal Basis, syndrome calculation circuit, BMA (Berlekamp-Massey algorithm), Chien search circuit, Galois Fields. |
Abstract |
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This paper presents a design and implementation of FPGA based Bose, Chaudhuri and Hocquenghem (BCH) codes for wireless communication applications. The codes are written in VHDL (Very High Speed Hardware Description Language). Here BCH decoder (15, 5, and 3) is implemented and discussed. And decoder uses serial input and serial output architecture. BCH code forms a large class of powerful random error correcting cyclic codes. BCH operates over algebraic structure called finite fields and they are binary multiple error correcting codes. BCH decoder is implemented by syndrome calculation circuit, the BMA (Berlekamp-Massey algorithm) and Chien search circuit. The codecs are implemented over cyclone FPGA device. |
Other Details |
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Paper ID: IJSRDV1I3068 Published in: Volume : 1, Issue : 3 Publication Date: 01/06/2013 Page(s): 665-668 |
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