Simulation of Single and Multilayer of Artificial Neural Network using Verilog |
Author(s): |
| Shaktivel S.M , VIT UNIVERSITY, Chennai-600 048 (Chennai-Tamil Nadu-INDIA); Rajesh Vasdadiya, VIT UNIVERSITY, Chennai-600 048 (Chennai-Tamil Nadu-INDIA); Shreyas J. Patel, VIT UNIVERSITY, Chennai-600 048 (Chennai-Tamil Nadu-INDIA) |
Keywords: |
| Neural Network, Verilog, Matlab, architecture |
Abstract |
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Artificial neural network play an important role in VLSI circuit to find and diagnosis multiple fault in digital circuit. In this paper, the example of single layer and multi-layer neural network had been discussed secondly implement those structure by using verilog code and same idea must be implement in mat lab for getting number of iteration and verilog code gives us time taken to adjust the weight when error become almost equal to zero. The purposed aim at reducing resource requirement, without much compromises on the speed that neural network can be realized on single chip at lower cost. |
Other Details |
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Paper ID: IJSRDV1I5011 Published in: Volume : 1, Issue : 5 Publication Date: 01/08/2013 Page(s): 1082-1085 |
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