Design of Efficient High Speed Vedic Multiplier |
Author(s): |
| Dr. Ajay Somkuwar , MANIT, Bhopal(M.P.); Dheeraj Jain, Dr. K. N. Modi University, Newai, Tonk (Raj.) |
Keywords: |
| Microprocessors, DSP, Communication applications, Vedic Multiplier, Vedic Mathematics. |
Abstract |
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Multipliers are extensively used in Microprocessors, DSP and Communication applications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. This paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. The work has proved the efficiency of Urdhva Triyagbhyam. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps. Urdhva tiryakbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large. |
Other Details |
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Paper ID: IJSRDV1I5030 Published in: Volume : 1, Issue : 5 Publication Date: 01/08/2013 Page(s): 1155-1157 |
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