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Implementation and Performance Analysis of a Vedic Multiplier Using Tanner EDA Tool


Dr. Ajay Somkuwar , MANIT, Bhopal(M.P.); Dheeraj Jain, Dr. K. N. Modi University, Newai, Tonk (Raj.)


Multiplier, Vedic algorithms, Vedic Mathematics, Tanner EDA, UrdhvaTriyakBhyam sutra.


high density, VLSI chips have led to rapid and innovative development in low power design during the recent years .The need for low power design is becoming a major issue in high performance digital systems such as microprocessor, digital signal processor and other applications. For these applications, Multiplier is the major core block. Based on the Multiplier design, an efficient processor is designed. Power and area efficient multiplier using CMOS logic circuits for applications in various digital signal processors is designed. This multiplier is implemented using Vedic multiplication algorithms mainly the "UrdhvaTriyakBhyam sutra., which is the most generalized one Vedic multiplication algorithm [1] . A multiplier is a very important element in almost all the processors and contributes substantially to the total power consumption of the system. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method . The schematic for this multiplier is designed using TANNER TOOL. Paper presents a systematic design methodology for this improved performance digital multiplier based on Vedic mathematics.

Other Details

Paper ID: IJSRDV1I5031
Published in: Volume : 1, Issue : 5
Publication Date: 01/08/2013
Page(s): 1158-1162

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