Compare "Urdhva Tiryakbhyam Multiplier" and "Hierarchical Array of Array Multiplier" |
Author(s): |
| Dr. Ajay Somkuwar , MANIT, Bhopal (M.P.); Dheeraj Jain, Dr. K. N. Modi University, Newai, Tonk (Raj.) |
Keywords: |
| Hierarchical array of array multiplier, Power Delay Product (PDP), Vedic Mathematics, Urdhva Tiryakbhyam. |
Abstract |
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Multipliers are extensively used in Microprocessors, DSP and Communication applications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. The need of high speed multiplier is increasing as the need of high speed processors are increasing. In this project, comparative study of different multipliers is done for high speed. The project includes two 4x4 bit Vedic Multiplier (VM) "Urdhva Tiryakbhyam multiplier" and "Hierarchical Array of Array Multiplier" of Ancient Indian Vedic Mathematics which are compared in terms of their speed. Urdhva Tiryakbhyam sutra increases the speed of multiplier by reducing the number of iterations then Hierarchical Array of Array Multiplier. |
Other Details |
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Paper ID: IJSRDV1I5050 Published in: Volume : 1, Issue : 5 Publication Date: 01/08/2013 Page(s): 1241-1245 |
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