A Single-Phase Clock Multiband Low-Power Flexible Divider |
Author(s): |
| Mrs. Haneefa , Kakatiya Institute of Technology & Science, Warangal; Mr. Narsimha Badri, Kakatiya Institute of Technology & Science, Warangal |
Keywords: |
| DFF, dual modulus prescaler, dynamic logic, E-TSPC, frequency synthesizer, high-speed digital circuits, true single-phase clock (TSPC), wireless LAN (WLAN). |
Abstract |
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In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers The frequency synthesizer was implemented using a charge-pump based phase-locked loop with a tri-state phase/frequency detector and a programmable pulse-swallow frequency divider. Since the required frequency of operation can be as high as 1.4GHz, the speed of the digital logic used in the frequency divider is a critical design factor. A custom library of digital logic gates was designed using MOS current-mode logic (MCML). These gates were designed to operate at frequencies up to 1.4GHz. This report outlines the design of the phase/frequency detector and the programmable pulse-swallow frequency divider. The design, layout, and simulation of the MCML logic family are also presented. |
Other Details |
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Paper ID: IJSRDV1I8008 Published in: Volume : 1, Issue : 8 Publication Date: 01/11/2013 Page(s): 1556-1560 |
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