Synthesis & FPGA Implementation of UART IP Soft Core |
Author(s): |
| Subir Maity , KIIT University, Bhubaneswar-751024, Odisha, India; Sohini Chatterjee, KIIT University, Bhubaneswar-751024, Odisha, India; Sona Gava, KIIT University, Bhubaneswar-751024, Odisha, India; Shreya Sharan, KIIT University, Bhubaneswar-751024, Odisha, India; Sonam Sinha, KIIT University, Bhubaneswar-751024, Odisha, India |
Keywords: |
| VERILOG, UART, XILINX, MODELSIM, Baud rate, Soft core. |
Abstract |
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this paper presents synthesis and hardware implementation of fully functional Universal Asynchronous Receiver Transmitter Intellectual Property core using XILINX SPARTAN-3 XC3S400 series FPGA. The UART soft core module consists of a transmitter along with baud rate generator and a receiver module with false start bit detection features. This has been implemented using VERILOG hardware description language and synthesized using XILINX ISE development tools. All behavioral simulation of UART module performed using MODELSIM simulator. After successful FPGA implementation transmitter and receiver module was tested by connecting FPGA board with Hyper Terminal software via RS232 interface at a data speed of 9.6 kbps. |
Other Details |
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Paper ID: IJSRDV1I9074 Published in: Volume : 1, Issue : 9 Publication Date: 01/12/2013 Page(s): 1992-1994 |
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