Multiply & Accumulate Unit using RNS algorithm & Vedic mathematics: A Review

High speed execution of arithmetic operations and high degree of precision in real time system are of major concern in any digital signal processing (DSP). Speed of DSP depends on speed of multiplier and algorithm used. In this paper we propose Residue Number System method for fast “carry free� floating point arithmetic operations. Floating Point RNS units have obvious advantages over traditional fixed point multiply & accumulate (MAC) units. Performance of multiplier is enhanced by VHDL implementation of Floating Point Multiplier using ancient Vedic mathematics. The Urdhva Tiryakbhyam sutra is applicable to all cases of multiplication. Any multi-bit multiplication can be reduced down to single bit multiplication and addition using this method. Using these formulas, the carry propagation from LSB to MSB is reduces due to one step generation of partial product. Thus enhanced speed of arithmetic operation is the key challenges in design of MAC using RNS algorithm & Vedic multiplier.