A Review of WISHBONE Bus Architecture and Comparison with On-chip Bus Architectures |
Author(s): |
| Bhankhar Dhvani , Gujarat Technological University ; Samir Shroff, Pronesis Technology |
Keywords: |
| WISHBONE, WISHBONE bus, WISHBONE interface, SoC buses |
Abstract |
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WISHBONE is an on-chip interconnection architecture used for communication between IP cores. WISHBONE bus used to interface variety of devices due to its open structural design and many a free IP core with a WISHBONE interface supplied by Open Core Association. Open Core SOC design methodology utilizes WISHBONE bus interface to foster design reuse by alleviating system-on-chip integration problems. In this paper an overview of WISHBONE bus architecture and a comparison with two other on-chip bus architectures (AMBA, CoreConnect) is presented. WISHBONE appears to be gaining more usage than other bus because of its performance parameters with flexibility, portability, reliability and addition data transfer cycle (RMW). WISHBONE is widely uses because its IP cores are freely available requiring neither any license agreement nor any registration. |
Other Details |
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Paper ID: IJSRDV2I10238 Published in: Volume : 2, Issue : 10 Publication Date: 01/01/2015 Page(s): 326-330 |
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