Low Power and High Speed CMOS Comparator for A/D Converter Applications - A Review |
Author(s): |
| Sweta Kumari , JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA, UP; Mr. Sampath Kumar V., JSSATE, NOIDA |
Keywords: |
| CMOS comparator, offset voltages, power consumption, SA-ADC, speed |
Abstract |
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In high-speed high-resolution analog to digital converters, comparators have a key role in quality of performance. High power consumption is one of the drawbacks of these circuits which can be reduced by using suitable architectures. Many versions of comparator are proposed to achieve desirable output in sub-micron and deep sub-micron design technologies. The selection of particular topology is dependent upon the requirements and applications of the design. Low power and high speed circuit design has emerged as a principal theme in today’s electronics industry. In this paper, a basic SA-ADC (successive approximation) is discussed as a proper choice for low power applications and comparison with other ADC architectures. Following with the study of design parameters of comparator, their architectures and its use in various applications. |
Other Details |
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Paper ID: IJSRDV2I10305 Published in: Volume : 2, Issue : 10 Publication Date: 01/01/2015 Page(s): 740-745 |
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