An Efficient Implementation of Floating Point Multiplier |
Author(s): |
| P.Suneel Kumar , VIDYA VIKAS INSTITUTE OF TECHNOLOGY; P.Swapna, HASVITA INSTITUTE OF MANAGEMENT AND TECHNOLOGY |
Keywords: |
| Floating Point Multiplication Algorithm, Hardware Of Floating Point Multiplier, Underflow/Overflow Detection |
Abstract |
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In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit. With latency of three clock cycles the design achieves 301 MFLOPs. The multiplier was verified against Xilinx floating point multiplier core |
Other Details |
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Paper ID: IJSRDV2I10363 Published in: Volume : 2, Issue : 10 Publication Date: 01/01/2015 Page(s): 770-773 |
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