A Novel Approach to Hardware Implementation of LDPC Codes Applicable in Image Processing |
Author(s): |
| Neelam Chaudhary , HCTM, Kaithal; Er. Rishi Pal, HCTM, Kaithal |
Keywords: |
| LDPC Codes, Hardware Implementation, FPGA, Cosimulation |
Abstract |
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Low density parity check (LDPC) codes are linear block codes used for error detection and correction mostly in high speed digital communication systems like digital broadcasting, optical fiber communications and wireless local area networks. LDPC codes have been subject to extensive research because of their significant performance in error correction. LDPC Code is a type of Block Error Correction code discovered and performance very close to Shannon’s limit .Good error correcting performance enables reliable communication. In this paper we have used a bit flipping algorithm to encode and decode the communication data. The input is a grayscale image and the output is verified using co-simulation between the MATLAB Simulink and QuestaSim. The FPGA implementation has done on the Xilinx 4 and the power consumption has calculated using Xilinx Power Analyzer. |
Other Details |
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Paper ID: IJSRDV2I12069 Published in: Volume : 2, Issue : 12 Publication Date: 01/03/2015 Page(s): 262-265 |
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