Low Power Minimization Technique and Strategies

Low power has emerged as a principal theme in today’s world of natural philosophy industries. Power dissipation has become a vital thought in terms of performance and space for VLSI Chip style. With shrinking technology, reducing power consumption and over all power management on chip area unit the key challenges below 100nm attributable to redoubled complexness. For several styles, improvement of power is vital as temporal arrangement attributable to the necessity to cut back package value and extended battery life. For power management leak current conjointly plays a vital role in low power VLSI styles. Leakage current is turning into an progressively vital fraction of the full power dissipation of integrated circuits. This paper describes regarding the assorted ways, methodologies and power management techniques for low power circuits and systems. A future challenge that has got to be met to style an occasional power high performance circuits are mentioned.