An Efficient CSLA Design by Using Modified Logic Formulation Method

Adders are widely used in most VLSI applications such as microprocessors and DSP applications to perform arithmetic functions. Carry select adder (CSLA) provides a good compromise between cost, area and performance among other high speed adders. In the existing method, fixed Cin bits are used for logic optimization of carry select (CS) and carry generation (CG) units. The CG unit which consists of separate CG units (CG0 & CG1) after that CS unit is used to design a CSLA structure. The proposed CSLA is designed by using modified logic formulation method which consists of CG0 & CG1 units are combined to form a single carry generate unit and the CS unit used only in every first bit for selecting the CG operations. The proposed CSLA is designed by using ripple carry adder (RCA), half sum generation (HSG), CG, CS and full sum generation (FSG). The synthesis results of the proposed methods show that it significantly reduces the area and delay than the existing CSLA. The simulation and synthesis results are obtained by using modelsim 6.4a and Xilinx 8.1i.