Generation of Random Numbers Using Advanced Well Method Based on Dual Port Memory

This paper presents a hardware architecture for efficient implementation of the well equidistributed long-period linear (WELL) algorithm. The design achieves a throughput of one sample per clock cycle and runs on a Xilinx FPGA device. The proposed advanced WELL architecture takes advantage of an Dual Port Ram (DPRAM) over Block Ram (BRAM). Our design is used to generate random numbers that are non-repeating in nature. The random numbers produced by our design are applied to the standard circuits to detect the faults in it. The use of Dual Port Ram (DPRAM) offers advantage like reduced access time, less occupancy of circuit board and lower power consumption. Comparative analysis between the two techniques has been made in respect to use of FPGA’s internal resources, maximum operating frequency and power consumption. The simulation result obtained using VHDL coding is also presented.