A Survey Paper on Design of STUMPS based Logic BIST Architecture |
Author(s): |
| Meha M. Panchal , V.G.E.C, Chandkheda; Prof. Kirit V. Patel, V.G.E.C, Chandkheda |
Keywords: |
| BIST, LFSR, MISR, SRSG, SISR, CUT, TPG, ORA, Logic BIST, STUMPS, at speed testing, scan test, PRPG, fault coverage, DFT. |
Abstract |
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Built-in self-test for logic circuits or logic BIST, is an effective solution for the test cost, test quality, and test reuse problems. The scheme is based on STUMPS (Self Test Using MISR and Parallel Shift register) architecture which uses an on-chip circuitry to generate the test patterns and analyze the responses with no or little help from an ATE. External operations are required only to initialize the Built-in tests and to check the test results. Expected output includes the designed STUMP based architecture, Which is test per scan using verilog HDL and simulation result having information of design is defect free or not. |
Other Details |
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Paper ID: IJSRDV2I1240 Published in: Volume : 2, Issue : 1 Publication Date: 01/04/2014 Page(s): 481-485 |
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