Analysis, Verification and Fpga Implementation of Low Power Inter Integrated Circuit Interface for Custom Asics |
Author(s): |
Jaswant Singh Rathore , Mewar University |
Keywords: |
FPGA, Low Power, I2C, ASICS |
Abstract |
This paper presents the design and simulation of an I2C (Inter-Integrated Circuit) serial interface. The design was described using the Verilog- hardware description language. The I2C Interface is intended for use in a family of integrated circuits (ICs) used in the detection of ionizing radiation. These custom ICs aid scientists in carrying out a wide variety of nuclear physics experiments. The ICs are being developed by the Integrated Circuit Design and were fabricated in a 5-Volt AMIS 0.5 μm, double-poly, tri-metal CMOS process (C5N). The current ICs only provide for analog outputs. Storing data in a digital format on chip before transmittal to a host computer via an I2C or "I2C-like" interface should result in improved system performance since the transmission of digital data is much less susceptible to interference form environmental noise. A large number of ICs are required in these types of instrumentation systems and therefore, at some point in the future, the I2C interface described herein will likely be incorporated along with an on-chip ADC and buffer RAM into second-generation versions of our current chips. The design of the proposed I2C interface was prototyped using inexpensive, readily-available Xilinx Spartan3E Starter development boards manufactured by Diligent. The prototype system consisted of two I2C "slaves" (emulating a pair of iii custom ICs) and an I2C "master". The "master" gathered results from the "slaves" and transmitted the data to a personal computer where it was displayed. The prototype system worked flawlessly at 100 KBits/sec but can accommodate up to 128 slaves. |
Other Details |
Paper ID: IJSRDV2I1359 Published in: Volume : 2, Issue : 1 Publication Date: 01/04/2014 Page(s): 759-761 |
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