New Approach for Advanced Encryption Standard (AES) Engines for Many-Core Processor Arrays |
Author(s): |
| A.KRISHNAKUMAR , THANTHAI PERIYAR GOVT. INSTITUTE OF TECHNOLOGY; prof.J.Vijaya, THANTHAI PERIYAR GOVT. INSTITUTE OF TECHNOLOGY; Dr.T.K.Shanthi, thanthai periyar govt institute of technology |
Keywords: |
| AES, Many Core Processor Array |
Abstract |
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The Advanced Encryption Standard (AES) has been lately accepted by NIST as the symmetric key standard for encryption and decryption of blocks of data. In encryption, the AES accepts a plaintext input, which is limited to 128 bits, and a key that can be specified to be 128 bits to generate the Cipher text. By exploring different granularities of AES as a onetime one Processor (OTOP), Small Encryption, Parallel Mixed Column and Full Parallelism we map these implementations on a field programmable gate array system. In comparison with published AES cipher implementations on general purpose processors. The proposed design has occupied less area and small delay. |
Other Details |
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Paper ID: IJSRDV2I2244 Published in: Volume : 2, Issue : 2 Publication Date: 01/05/2014 Page(s): 552-557 |
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