Analysis and realization of a Viterbi decoder with low power dissipation |
Author(s): |
| Patel Pratik J. , M.Tech (Purs.) CGPIT, Maliba Campus, UTU; Tarunkumar C. Lad, M.E at SVNIT, SURAT |
Keywords: |
| convolutional encoder, Forward Error correction, Xilinx, RTL simulation, SPRTAN 3E FPGA |
Abstract |
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In this paper, a low-power design of Viterbi decoders at the gate level in the standard cell design environment is proposed. In the standard cell design environment, the behavior of a design is described in a high-level hardware description language, such as VHDL or Verilog. The behavioral design is synthesized to generate a gate level design. The gate-level design is placed and routed to generate a layout of the design. The focus of our research in the low-power design of Viterbi decoders at logic level is reduction of dynamic power dissipation in the standard cell design environment. We considered two methods, clock-gating and toggle-filtering, in our design. |
Other Details |
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Paper ID: IJSRDV2I2397 Published in: Volume : 2, Issue : 2 Publication Date: 01/05/2014 Page(s): 983-989 |
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